This invention relates to MOS switching devices, and particularly to such devices having a shield gate for reducing switching noise.
Heretofore, photosensitive image arrays were switched through access transistors associated with each photosensitive element as shown in FIG. 1 (Prior Art). The prior art doublegated access switch 10 has two separate switching structures in series: a P-channel row, transistor 12R with a source 14R, a drain 16R, a row select gate 18R; and a P-channel column transistor 12C with a source 14C, a drain 16C, and a column select gate 18C. A photo diode 20 from the array is connected to row source 14R of each access switch. Diode 20 is charged by a reverse bias voltage and discharges, accumulating holes in response to incident radiation 22. The amount of discharge or hole accumulation on each diode 20 during the exposure period is a function of the intensity of light at that element of the image array. Access switches 10 are sequentially selected by a scanning device (not shown) and the accumulated charge flows through simultaneously activated row transistor 12R and column transistor 12C to form a read out current at common output 24 connected to each column drain 16C. The readout time per array element is short, about one micro second, and the accumulated charge is small, about two picocoulombs (one picofarad diode capacitance at two volts). The readout time and readout charge are sufficiently small that transient effects encountered in turning on access device 10, especially column transistor 12C, are significant. Row transistor 12R is selected first and has attained a steady state, dc bias condition when column transistor 12C is turned on. The start-up transients in row transistor 12R have expired prior to the discharge of diode 20 through access switch 10. The start-up transients of column transistor 12C however, occur simultaneously with the readout current and significantly affect the total current at output 24. This transient noise current has two primary factors: a charging current generated by the gate 18C to drain 16C capacitance which charges immediately after turnon, and a depletion current generated as the drain depletion region 26 is formed in column transistor 12C. A typical gate-to-drain capacitance of transistor 12C is about 0.03 picofarads, causing a signal-to-noise ratio of about 30. The low light level light end of the dynamic range is severely limited by this capacitance.
In addition the S/N ratio varies drastically between access switches 10 .fwdarw. because the Miller capacitances are not uniform. This capacitance is inversely proportional to the gate 18C-to-drain 16C spacing. The gatedrain overlap region 28 provides the majority of the capacitance because along overlap 24 the capacitance spacing is the closest, limited only by the thickness of silicon oxide 30 which is typically 0.1 microns. Overlap 28 is kept to a minimum to reduce the Miller capacitance and is only tolerated because a nominal amount of overlap is required to properly locate depletion region 26. Any slight lateral shift of gate 18C relative to drain 16C between access devices causes great changes in the overlap portion of the capacitance. For instance: a one micron overlap has a mean spacing of 0.1 micron and a capacitance of 0.03 picofarads; a zero micron overlap has a mean spacing of about 1.0 microns causing a capacitance drop of 90% from the one micron overlap capacitance; and a one micron underlap has a mean spacing of about 2.0 microns causing a capacitance drop of 95% from the one micron overlap capacitance. Small misalinement errors in overlap 28 produce great changes in gate-to-drain capacitance. Mask alignment error in manufacturing access switches 10 is typically about three microns. Self-alignment techniques reduce this error to about one micron. However, self-alignment techniques involve diffusion temperatures in excess of 1000.degree. C. and are not applicable to devices requiring aluminum which evaporates at 600.degree. C. Even with self-alignment techniques the one micron error causes the S/N ratio to vary by a factor of 10 to 1 between access switches 10.